1. Field of the Invention
The invention relates to a data exchange system, and more particularly to a data exchange system to be used for a mobile communication base station applicable to high traffic. The invention relates further to a method of data exchange.
2. Description of the Related Art
A mobile communication base station is generally designed to have a plurality of central processing units (CPUs) for processing subscriber data to thereby conform to high traffic. A relation among the number of subscriber""s loops M, subscriber data processing capability per a single central processing unit L, and the number of central processing units N is represented by the following equation.
M=Lxc3x97N
A generally used data exchange system is explained hereinbelow with reference to FIG. 1 which is a block diagram of a mobile communication base station including a generally used data exchange system.
First, data flow from a subscriber to public network is explained hereinbelow. As illustrated in FIG. 1, the m number of data about subscriber""s loop is transmitted from a subscriber radio interface circuit 61 to each of n CPUs 1-i (i=1 to n). Data received 1-i is processed in each of n CPUs and then transmitted to a parallel/serial (P/S) converting circuit 63 as parallel data PDTi (i=1 to n). The parallel data is converted into the m number of serial data SDATj (j=1 to m) by the P/S converting circuit 63, and then, is line-exchanged in a line exchange circuit 64. The thus line-exchanged serial data SDATjxe2x80x2 (j=1 to m) is output to public lines 65 through a public network interface circuit 62.
Data flow from public network to a subscriber is just opposite to the above-mentioned steps. The detail is omitted.
Hereinbelow is explained the function of a section encompassed with a broken line in FIG. 1 and including the P/S converting circuit 63 and the line exchange circuit 64. Herein, suppose that data is transmitted from a subscriber toward public network. Parallel data PDTi (i=1 to n) transmitted from a subscriber through a plurality of CPUs 1-1 to 1-n is in a row, xe2x80x9cD11-17xe2x80x9d, xe2x80x9cD21-27xe2x80x9d, - - - , xe2x80x9cDL1-L7xe2x80x9d, xe2x80x9cDxe2x80x211-17xe2x80x9d, - - - , as illustrated in FIG. 2. The parallel data PDTi is temporarily stored in a buffer formed in the P/S converting circuit 63, and then, is transmitted from the circuit 63 as the M number of serial data SDAT i1-iL wherein M=Nxc3x97L.
The thus transmitted SDAT i1-iL is line-exchanged to a desired line by the line exchange circuit 64. The thus line-exchanged M number of serial data is transmitted to the public network interface circuit 62, and then, to the public lines 65 through the public network interface circuit 62. Herein, SDAT i1 to SDAT nL indicates the totally M number of data.
The structure of a first conventional data exchange system is explained hereinbelow with reference to FIG. 3.
As illustrated in FIG. 3, the first conventional data exchange system is comprised of the P/S exchange circuit 63 and the line exchange circuit 64. The P/S exchange circuit 63 includes a large-size dual port RAM 631 for storing therein data having been processed in the n CPUs 1-1 to 1-n, a parallel/serial (P/S) converting section 632, a timing generating circuit 633, and a bus arbitrating circuit 634 for arbitrating a bus from the n CPUs. The line exchange circuit 64 includes a switching circuit 641, and an exchange information transfer circuit 642. Parts or elements corresponding to those in FIG. 1 have been provided with the same reference numerals.
The dual port RAM 631 includes the m number of storage areas in which parallel data transmitted from the n number of CPUs 1-1 to 1-n is to be stored, and further includes ports each of which faces the n number of CPUs and the P/S converting section 632. Data is stored (or written) into or taken (or read) out of the dual port RAM 631 through the ports. The dual port RAM 631 is in communication with all of the n number of CPUs 1-1 to 1-n through a common data bus DBUS, and receives addresses ADD from all of the n number of CPUs 1-1 to 1-n.
The P/S converting section 632 converts parallel data PDT received from the dual port RAM 631, into serial data at a timing defined by a timing signal TIM transmitted from the timing generating circuit 633. The P/S converting section 632 transmits parallel address PAD to the dual port RAM 631.
The timing generating circuit 633 produces timing signals TIM at a certain interval, and transmits it to the P/S converting section 632 for converting parallel data into serial data.
The switching circuit 641 connects serial data received therein to a designated public line in accordance with exchange information XC transmitted from the exchange information transfer circuit 642.
The exchange information transfer circuit 642 receives the exchange information XC from an upstream system (not illustrated), and transmits the exchange information XC to the switching circuit 641 at a predetermined timing.
The bus arbitrating circuit 634 arbitrates requests transmitted from the n number of CPUs 1-1 to 1-n for storing parallel data therein, and prevents data collision on a bus. Specifically, the bus arbitrating circuit 634 receives requests RQ1-RQn for occupying a bus from the n number of CPUs 1-1 to 1-n, and transmits an allowance AK1-AKn to use a bus.
Hereinbelow is explained an operation of the first conventional data exchange system illustrated in FIG. 3, with reference to FIG. 4 which is a time chart illustrating an operation of the first conventional data exchange system. Each of the n number of CPUs 1-1 to 1-n, when having processed data, transmits the request RQ1-RQn for occupying the data bus DBUS of the dual port RAM 631, to the bus arbitrating circuit 634. The bus arbitrating circuit 634 having received those requests RQ1-RQn for occupying the data bus DBUS of the dual port RAM 631 transmits the allowance AK1-AKn to each of the CPUs in an order at which the requests RQ1-RQn have been received. Only CPU which received the allowance can transmit the processed data to the dual port RAM 631 through the data bus DBUS. The thus transmitted, processed data is stored in the dual port RAM 631. The data having been stored in the dual port RAM 631 is taken out of the dual port RAM 631 as the parallel data PDT by the P/S converting section 632 in synchronization with the timing signals TIM transmitted from the timing generating circuit 633 for every one of the m number of lines in accordance with the parallel address PAD transmitted from the P/S converting section 632. The thus taken-out parallel data PDT is converted into serial data in the P/S converting section 632. The m number of data having been converted into serial data in the P/S converting section 632 is line-exchanged in the switching circuit 641 in accordance with the exchange information XC transmitted from the exchange information transfer circuit 642 and indicating where the data is transferred to. The thus line-exchanged data is transmitted to the public network interface circuit 62 as serial data SDAT1xe2x80x2 to SDATmxe2x80x2.
The switching circuit 641 carries out switch between input and output lines in such a manner as illustrated in FIG. 5. Specifically, the switching circuit 641 converts data D1, D2 and Dm received therein through input lines, into data D1xe2x80x2, D2xe2x80x2 and Dmxe2x80x2 to be output through output lines. As illustrated in FIG. 5, data D1xe2x80x2, D2xe2x80x2 and Dmxe2x80x2 correspond to data Dm, D1 and D2, respectively.
FIG. 6 illustrates a second conventional data exchange system, including the P/S exchange circuit 63 and the line exchange circuit 64. The illustrated data exchange system is different from the first conventional data exchange system illustrated in FIG. 3 in that it includes data buffers 2-1 to 2-n in the same number as that of the CPUs 1-1 to 1-n, in place of the dual port RAM 631 and the bus arbitrating circuit 634. The data buffers 2-1 to 2-n are associated with the CPUs 1-1 to 1-n one to one. Similarly to the first conventional data exchange system illustrated in FIG. 3, the second conventional data exchange system illustrated in FIG. 6 is comprised of the P/S exchange circuit 63 and the line exchange circuit 64, wherein the P/S exchange circuit 63 includes, a parallel/serial (P/S) converting section 632, and a timing generating circuit 633, as well as the data buffers 2-1 to 2-n, and the line exchange circuit 64 includes a switching circuit 641, and an exchange information transfer circuit 642. Each of the CPUs 1-1 to 1-n is connected to an associated data buffer through a data bus DBUS1-DBUSn, and transmits an address ADD1-ADDn to an associated data buffer. Each of the data buffers 2-1 to 2-n transmits parallel data PDT1-PDTn to the P/S converting section 632.
Each of the data buffers 2-1 to 2-n temporarily stores parallel data transmitted from an associated CPU, and acts as a memory for making it possible to conform to a timing designated by the P/S converting section 632.
Hereinbelow is explained an operation of the second conventional data exchange system, with reference to FIG. 7 which is a time chart illustrating the operation.
Each of the n number of CPUs 1-1 to 1-n, when having finished processing data, stores the thus processed data in an associated data buffer 2-1 to 2-n through an associated data bus DBUS1-DBUSn, designating an address with an address bus ADD1-ADDn. The thus stored parallel data PDT1-PDTn is transmitted to the P/S converting section 632 for every one of the m number of lines in synchronization with timing signals TIM transmitted from the timing generating circuit 633, and then converted into serial data by the P/S converting section 632.
The thus converted m number of serial data is line-exchanged in the switching circuit 641 in accordance with the exchange information XC transmitted from the exchange information transfer circuit 642 and indicating where the serial data is transferred to. The switching circuit 641 carries out switching in such a manner as illustrated in FIG. 5. Specifically, the switching circuit 641 converts data SDAT1, SDAT2 and SDATm received therein, into data SDAT1xe2x80x2, SDAT2xe2x80x2 and SDATmxe2x80x2. As illustrated in FIG. 5, data SDAT1xe2x80x2, SDAT2xe2x80x2 and SDATmxe2x80x2 correspond to data SDATm, SDAT1 and SDAT2, respectively. Thus, the serial data SDAT1xe2x80x2 to SDATmxe2x80x2 is transmitted to the public lines from the switching circuit 641.
The above-mentioned conventional data exchange systems are accompanied with the following problems.
First, the first conventional data exchange system illustrated in FIG. 3 does not independently use a data bus for each of the CPUs 1-1 to 1-n when the processed data is transferred from each of the CPUs 1-1 to 1-n to the dual port RAM 631. Hence, the data is transferred to the dual port RAM 631 in time-sharing manner for each of the CPUs 1-1 to 1-n. This causes a problem that it would take much time to transfer data from each of the CPUs 1-1 to 1-n to the dual port RAM 631, as data is increased in an amount, namely, the number of CPUs is increased.
In addition, the first conventional data exchange system needs the bus arbitrating circuit 634 as a dedicated circuit, which causes a problem that the data exchange system cannot avoid becoming larger in size.
Furthermore, since the first conventional data exchange system includes the switching circuit 641 for line-exchange, the data exchange system would become larger in size as the number of lines is increased.
The second conventional data exchange system illustrated in FIG. 6 independently uses the data buffer 2-1 to 2-n for each of the CPUs 1-1 to 1-n. Hence, time loss is not generated for data transfer in the data exchange system. However, the data buffer might be increased in size in dependence on capability per CPU for processing subscribers"" data, which is accompanied with a problem that the second conventional data exchange system illustrated in FIG. 6 is also increased in size.
It may be considered that a dual port RAM is substituted for the data buffer. However, in such a case, each of the CPUs has to be connected to the P/S converting circuit through an address line. Namely, the data exchange system is required to include the n number of address lines similar to the parallel address PAD illustrated in FIG. 3. This increases the number of signals, which causes the data exchange system to have a more complex structure.
Furthermore, since the second conventional data exchange system includes the switching circuit 641 for line-exchange similarly to the first conventional data exchange system, the second conventional data exchange system would become larger in size as the number of lines is increased.
Japanese Unexamined Patent Publications Nos. 4-252345 and 6-54022 have suggested apparatuses and methods for transferring data through a dual port RAM. However, the above-mentioned problems in the first and second conventional data exchange systems cannot be solved by those apparatuses and methods.
In view of the foregoing problems of the conventional data exchange systems, it is an object of the present invention to provide a data exchange system which can be fabricated in a smaller size than the conventional ones. Specifically, it is an object of the present invention to provide a data exchange system including no line exchange circuit which is a major factor for causing a data exchange system to become larger in size. It is also an object of the present invention to provide a method of data exchange providing the same advantages as those of the above-mentioned inventive data exchange system.
In one aspect of the present invention, there is provided a data exchange system including (a) a plurality of control circuits, (b) a plurality of memories each of which stores data transmitted from an associated control circuit, (c) a designator for providing each of the memories a designation about an area in an associated memory in which the data is to be written, and (d) a reader for reading out data written in the designated area in the associated memory.
The data exchange system may further include an exchange information transfer circuit for transmitting exchange information to each one of the control circuits, the data being written into an area in an associated memory in accordance with the exchange information
There is further provided a data exchange system including (a) a plurality of control circuits, (b) a plurality of memories each of which stores data transmitted from an associated control circuit, (c) an exchange information transfer circuit for transmitting exchange information to each one of the control circuits, (d) a timing pulse generating circuit for providing each of the memories a designation about an area into which the data is to be written, and (e) a reading circuit for reading out data written in the thus designated area in the associated memory.
The data exchange system preferably includes the memories in the same number as that of the control circuits in such a manner that the memories are associated with the control circuits one to one. It is preferable that each one of the memories has R storage areas where R is a positive integer equal to or greater than 2, and wherein the designator or timing pulse generating circuit designates the R storage areas one by one as an area in which the data is to be written. It is also preferable that each of the R storage areas comprises a plurality of sections. Each of the R storage areas preferably has the sections in the same number as that of lines to which the data transmitted from the control circuits is to be transmitted.
It is preferable that each one of the memories comprises a dual port random access memory (RAM) having first and second ports, data transmitted from the control circuits being written into the memories through the first port, and the thus written-into data being read out by the reader or reading circuit through the second port. For instance, the first port may be designed as a serial port, and the second port as a parallel port. There may be used a central processing unit (CPU) as the control circuit.
It is preferable that the designator or timing pulse generating circuit is designed to transmit selection signals to the memories to thereby monitor access from the control circuits to the memories. For instance, the designator or timing pulse generating circuit may be designed to monitor at a certain interval which one of the first and second storage areas of the memories each of the control circuits makes access to, and transmits selection signals based on monitoring results so that the reader or reading circuit can read out the data written in one of the first and second storage areas.
It is preferable that the reader or reading circuit includes a parallel/serial converting circuit for converting parallel data transmitted from the memories to serial data, and an address counter for transmitting a load pulse to the parallel/serial converting circuit and an address to the memories. It is preferable that all of the memories are in communication with the parallel/serial converting circuit through a common bus.
It is preferable that the designator or timing pulse generating circuit includes (a) address decoders in the same number of the control circuits, each of the address decoders decoding an address an associated control circuit made access to, (b) access point latches in association with the address decoders, each of the access point latches storing therein a result of decoding made by an associated address decoder, and (c) a selection signal generating circuit for transmitting selection signals to the memories, based on the result stored in each one of the access point latches. Each of the access point latches preferably includes (a) at least one flip-flop having a first input terminal fixed at a high level, a second input terminal receiving a decode output transmitted from an associated address decoder, and an output terminal for transmitting an output in accordance with the decode output, (b) a plurality of bit latches for latching the output transmitted from the flip-flop, (c) at least one selector receiving outputs transmitted from the bit latches and transmitting a single output, and (d) a bit selector for latching the output transmitted from the selector. The access point latches may include the bit latches in the same number as the number of areas into which each one of the memories is divided. For instance, the number is two.
The data exchange system may further include an inverter for inverting a signal, and wherein a first bit latch is activated when receiving a signal, and a second bit latch is activated when receiving an inverted signal inverted by the inverter.
In another aspect of the present invention, there is provided a method of data exchange, including the steps of (a) designating each one of control circuits an area into which data is to be written, (b) storing data transmitted from one of the control circuits, in the thus designated area in one of memories, and (c) reading out the data stored in the designated area in the one of memories.
It is preferable in the method that each one of the memories is in association with each one of the control circuits, and the data transmitted from one of the control circuits is stored in the designated area in an associated memory. It is preferable that each one of the memories has first and second storage areas, and that the method further include the step of alternately designating the first and second storage areas as an area in which the data is to be written. It is preferable that each of the first and second storage areas comprises a plurality of sections, and that the method further include the step of designating at least one of the sections for the data to be written thereinto. It is also preferable that each one of the memories has R storage areas where R is a positive integer equal to or greater than 2, and that the method further includes the step of designating the R storage areas one by one as an area in which the data is to be written. It is also preferable that each of the R storage areas has a plurality of sections, and that the method further include the step of designating at least one of the sections for the data to be written thereinto.
The method may further include the step of providing exchange information to each one of the control circuits, the data being written into the designated area in the one of memories in accordance with the exchange information.
The method may further include the step of monitoring access from the control circuits to the memories.
The method may further include the step of converting parallel data transmitted from the memories to serial data, in which case it is preferable that the parallel data is transmitted from all of the memories through a common bus.
The method may further include the steps of monitoring at a certain interval which one of the first and second storage areas of the memories each of the control circuits makes access to, and transmitting selection signals based on monitoring results so that the data written in one of the first and second storage areas can be read out. For instance, the first storage area may be selected by receiving a first signal, and the second storage area may be selected by receiving a second signal which is an inverted signal of the first signal.
It is preferable that the above-mentioned step (a) further includes (a-1) decoding an address each one of the control circuit made access to, (a-2) storing therein a result of decoding carried out in the step (a-1), and (a-3) transmitting selection signals to the memories, based on the result of decoding.
In brief, the data exchange system in accordance with the present invention includes a plurality of memories in association with each one of control circuits or CPUs. A signal is transmitted to each one of control circuits or CPUs in accordance with exchange information to thereby designate an area into which data is to be written. Then, data written into the designated area is read out. This structure makes it possible to eliminate a line exchange circuit to thereby decrease the data exchange system in size.
The above and other objects and advantageous features of the present invention will be made apparent from the following description made with reference to the accompanying drawings, in which like reference characters designate the same or similar parts throughout the drawings.